| 摘要 |
A parallel read/write circuit for use with a plurality of transducer head assemblies and method of operation thereof. The parallel read/write circuit includes a parallel read/write cache, e.g., a bidirectional parallel-serial converter buffer in one advantageous embodiment. A byte-to-bit disassembler, coupled to the parallel read/write cache, receives parallel data from the parallel read/write cache and transmits each bit of the parallel data to a separate transducer head assembly, where each bit of the parallel data is written onto a different disk surface of a recording medium at substantially the same time. In an advantageous embodiment, the byte-to-bit disassembler is a parallel in/parallel out shift register. The parallel read/write circuit also includes a bit-to-byte assembler, coupled to the parallel read/write cache and the transducer head assemblies, that combines a plurality of data bits into parallel data form, wherein each of the data bits is read from a separate disk surface of the recording medium at substantially the same time. In an advantageous embodiment, the bit-to-byte assembler is a parallel in/parallel out shift register. Alternatively, in another advantageous embodiment, both the bit-to-byte assembler and the byte-to-bit disassembler are the same device.
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