Variable voltage data buffers

摘要

A data buffer circuit includes first and second driver circuits coupled to the data latch circuit and operative to respectively pull up and pull down their outputs towards respective first and second voltages responsive to first and second data signals. An output circuit includes first and second transistors connected at an output node and operative to respectively pull up and pull down the output node toward respective ones of the first and second voltages responsive to respective ones of the outputs of the first and second driver circuits. A transition compensation circuit is operative to control relative rates at the output node of the output circuit transitions toward the first and second voltages responsive to a transition rate control signal.