| 摘要 |
A semiconductor memory device comprising a plurality of memory cells to store data, k data input/output lines (k=a natural number), a plurality of sense amplifiers which are provided in n number (n=a natural number) for the k data input/output lines, and perform reading and writing cell data for the plurality of memory cells, a column selection gate which selects one sense amplifier among the n sense amplifiers, and connects the selected sense amplifier to the corresponding data input/output line, a selector circuit which controls the column selection gate, and sequentially selects m sense amplifiers (m=1, 2, . . . , n) among the n sense amplifiers, and a switching circuit which changes the order of selecting the m sense amplifiers by the selector circuit.
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