| 摘要 |
A delay locked loop (DLL) for use in a semiconductor device includes a phase detector that receives a reference clock signal and a feedback clock signal and provides a delay control signal to a latch. The latch provides a latched delay control signal to a delay circuit. The delay circuit receives the reference clock signal in addition to the latched delay control signal, and provides a delayed clock signal. An off chip driver (OCD) receives the delayed clock signal and provides an interim feedback clock signal to a receiver. The receiver provides the feedback clock signal to the phase detector, thus completing the loop. The DLL may also include a means for receiving and responding to an update command, wherein the update command causes loop to open, and the latch to store the delay control signal.
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