| 摘要 |
<p>The invention relates to a process for synchronizing a computer system with regard to a date which changes over time. The computer system comprises one or more modules (1, 2, 3, 4), each module (1, 2) comprising several processors (10, 11, 12, 13, 20, 21, 22, 23) regulated by a clock specific to a module (1, 2). Each processor (10, 11, 12, 13, 20, 21, 22, 23) comprises a private register TBR (16, 17, 18, 19, 26, 27, 28, 29) adapted to contain a value corresponding to said date and to undergo an incrementation by the clock specific to the module (1, 2) comprising this processor (10, 11, 12, 13, 20, 21, 22, 23). A processor (10) is selected as the master of the system so as to instruct each of the other processors (11, 12, 13, 20, 21, 22, 23) which function as a salve to place the master processor and to declare said master processor in a ready state which consists, for each slave processor (11, 12, 13, 20, 21, 22, 23), in waiting for an authorization from the master processor (10) of the system, without being able to be interrupted. Each processor (10, 11, 12, 13, 20, 21, 22, 23) possessing the said authorization, immediately reads the contents of a register TBC (50, 51) common to the processors (10, 11, 12, 13, 20, 21, 22, 23) of one and the same module (1, 2) and writes these contents to an associated register (16, 17, 18, 19, 26, 27, 28, 29) TBR without being able to be interrupted.</p> |
