发明名称
摘要 PURPOSE: A method for manufacturing a transistor is provided to be capable of preventing short channel effect and GIDL(Gate Induced Drain Leakage). CONSTITUTION: A gate electrode(35) with a gate insulating layer(33) and an insulating spacer(37) is formed on a semiconductor substrate(31). A trench is formed by selectively etching the exposed substrate. Lightly doped n-type impurity ions are implanted to the trench. The first epitaxial layer(43) is then grown in the trench. A source/drain region is formed by implanting heavily doped n-type impurity ions into the first epitaxial layer(43). A plug(47) is formed by growing the second epitaxial layer on the first epitaxial layer.
申请公布号 KR100419024(B1) 申请公布日期 2004.02.21
申请号 KR20020042117 申请日期 2002.07.18
申请人 发明人
分类号 H01L21/336 主分类号 H01L21/336
代理机构 代理人
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