发明名称 POWER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a power circuit which can raise the conversion efficiency by preventing a through current from flowing from high side to low side. SOLUTION: This power circuit has a DC-DC converting circuit I(QP1, QN1, L1, and C0) which has a PMOS(QP1) and an NMOS(QN1) and gets PWM-controlled DC output voltage by switching them on alternately by PWM signals, an error amplifier 40 which gets an error signal by comparing the output of the above DC-DC converting circuit with a reference voltage value, and PWM means (31A and 32) which generate PWM signals with their pulse width controlled by the above error signals and supply them to each gate of the above DC-DC converting circuit. An output driver 31A constituting the above PWM means switches on the NMOS(QN1) after the PMOS(QP1) is switched off surely by switching on the NMOS(QN1) when the middle node potential VMA comes to specified potential or under after the PMOS(QP1) is switched off. Also, it switches on the PMOS(QP1) after the NMOS(QN1) is switched off. As a result, the PMOS(QP1) and the NMOS(QN1) are not switched on concurrently and a through current never flows. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004056983(A) 申请公布日期 2004.02.19
申请号 JP20020215246 申请日期 2002.07.24
申请人 SEIKO EPSON CORP 发明人 NISHIMAKI TATSUO
分类号 H02M3/155;H02M1/38;H02M3/158;H03K17/16;H03K17/687;(IPC1-7):H02M3/155 主分类号 H02M3/155
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