发明名称 SYSTEM OPERATION MONITORING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a system operation monitoring circuit capable of allowing flexibility to a system design and of enabling application to the case that safety is strongly required. SOLUTION: The system is provided with A WDT (watch dog timer) counter 12 which is variable and for monitoring a normal operation of a system mounting CPU 1 including system software and can set a time voluntarily until system abnormality is detected. Also, the system is equipped with the circuit with a clock stop detection circuit for monitoring a clock for the WDT counter 12 operation, thereby generating interruption to the CPU 1 by clock stop detection and outputting an emergency stop-signal. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004054729(A) 申请公布日期 2004.02.19
申请号 JP20020213425 申请日期 2002.07.23
申请人 YASKAWA ELECTRIC CORP 发明人 TAKAYAMA SHIGENORI
分类号 G06F11/30;(IPC1-7):G06F11/30 主分类号 G06F11/30
代理机构 代理人
主权项
地址