BACK GATE AND BOTTOM LAYER INTERCONNECT FOR ACTIVE MATRIX DISPLAYS

摘要

Active matrix displays include transistors having a top gate row line (208) and a bottom gate row line (212). The bottom gate row line is situated below the top gate row line and can be driven in parallel with the top gate row line (208). The bottom gate row line (212) can be formed as a patterned refractory conductor that is covered with a dielectric layer (216). A transistor active layer, gate oxide, and top row line are formed on top of the dielectric layer (216).