发明名称 |
Semiconductor integrated circuit device and method for manufacturing the same |
摘要 |
The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL1, BL2 are, respectively, 2 Omega/□or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL1, BL2 by which the number of the steps of manufacturing the DRAM can be reduced.
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申请公布号 |
US2004031980(A1) |
申请公布日期 |
2004.02.19 |
申请号 |
US20030642743 |
申请日期 |
2003.08.19 |
申请人 |
NARUI SEIJI;UDAGAWA TETSU;KAJIGAYA KAZUHIKO;YOSHIDA MAKOTO |
发明人 |
NARUI SEIJI;UDAGAWA TETSU;KAJIGAYA KAZUHIKO;YOSHIDA MAKOTO |
分类号 |
H01L21/768;H01L21/822;H01L21/8242;H01L27/10;H01L27/108;(IPC1-7):H01L29/76;H01L31/119 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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