DRAM circuit has refresh sequence adjusting device with electrically programmable trim circuit in which frequency-determining network fuse elements are selectively changed to set state by overvoltage

摘要

The DRAM circuit has memory cells and an access controller, a refresh device and a trim circuit for adjusting the refresh oscillator frequency to a desired value with an electrically programmable trim circuit in which fuse elements of a frequency-determining network are selectively changed from an unset state to a set state by applying an overvoltage and a fuse selection device for connecting an overvoltage source in accordance with selection. The Dynamic Random Access Memory or DRAM circuit has a number of memory cells (21) and an access controller (22), a refresh device (24) and a trim device (30,40,60,70) for adjusting the refresh oscillator (25) frequency to a desired value with an electrically programmable trim circuit (30) in which fuse elements of a frequency-determining network are selectively changed from an unset state to a set state by applying an overvoltage and a fuse selection device (70) for connecting an overvoltage source in accordance with selection data. AN Independent claim is also included for the following: (a) a method of adjusting the oscillation frequency of the refresh oscillator for a DRAM circuit.