发明名称 INTEGRATED CIRCUIT AND METHOD FOR GENERATING ITS REDUNDANCY RELIEVING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To improve redundancy relief efficiency in an integrated circuit provided with a plurality of memory macro-blocks. SOLUTION: A defective address discriminating section 4 stores the addresses of defective memory cells included in a plurality of memory macro-blocks. When an address specified by macro-selecting signals SL1, SL2 and address data ADD coincide with stored addresses, the section 4 outputs defective address detecting signals SDT1, SDT2 indicating stop of data output to the blocks 1, 2 including defective memory cells, and specifies a redundant address RAD to a redundant memory macro-block 3. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004055094(A) 申请公布日期 2004.02.19
申请号 JP20020214839 申请日期 2002.07.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 AKAMATSU HIRONORI;KURUMADA MAREFUSA
分类号 G11C29/04;G11C29/00;(IPC1-7):G11C29/00 主分类号 G11C29/04
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