| 摘要 |
PROBLEM TO BE SOLVED: To provide a buffer circuit for reducing propagation delay time which is suitable for a clock tree buffer. SOLUTION: Two transistors (PM1, NM1), whose ON/OFF states are controlled by signal values at the control terminals thereof, are serially connected between a first and a second power supplies. The connection point between those two transistors is connected to an output terminal (OUT), and the control terminal of the transistor (PM1) is connected to an input terminal (IN). A circuit is provided for controlling ON/OFF state of the transistor (NM1) by an input signal from the input terminal (IN). This circuit turns the transistor (NM1) off when the input signal is at a second logical level corresponding to the second power supply, turns the transistor (NM1) on when the input signal makes transition to a first logical level corresponding to the first power supply, causes the output terminal (OUT) to make transition to the second power supply voltage side, and then turns the transistor (NM1) off. When the input signal makes transition from the first to the second logical level and the transistor (PM1) makes transition from OFF to ON state, the transistor (NM1) is turned off, and a flip-flop (INV2, INV3) is connected to the output terminal (OUT). COPYRIGHT: (C)2004,JPO
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