发明名称 METHOD OF PLATING CONNECTING LAYER FOR CIRCUIT PATTERN OF PRINTED CIRCUIT BOARD
摘要 PROBLEM TO BE SOLVED: To provide a method of plating connecting layer by which a connecting layer used on the circuit pattern of a printed circuit board can be electroplated, without providing bus trace. SOLUTION: After a substrate 10, provided with a circuit pattern 20 having connections 22 and plating sections 24, is prepared, a masking layer 30 which covers the circuit pattern 20 is formed on the substrate 10, and the connections 22 and plating sections 24 of the pattern 20 are exposed by opening prescribed portions of the masking layer 30. Then a conductive layer 50 is formed on the masking layer 30 and is electrically connected to the circuit pattern 20 through the connections 22. In addition, a second masking layer 30 is formed on the conductive layer 50 and the plating sections 24 of the circuit pattern 20 are exposed, by opening prescribed portions of the second masking layer 30. Thereafter, connecting layers 22 are electroplated at the plating sections 24 of the circuit pattern 20, and the second masking layer 30 and conductive layer 50 are successively removed. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004055893(A) 申请公布日期 2004.02.19
申请号 JP20020212549 申请日期 2002.07.22
申请人 S & S TECHNOLOGY CORP 发明人 SU KYOKA;BA SOJIN;CHI MANKOKU
分类号 C25D5/02;C23F1/18;C25D7/00;H05K3/06;H05K3/18;(IPC1-7):H05K3/18 主分类号 C25D5/02
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