| 摘要 |
A communication data processing circuit is provided that suitably controls an on/off operation of clock signals, thus effectively reducing the power consumption. The communication data processing circuit processes communication data based on a clock signal to be input. The communication data processing circuit includes a packet processing section 30 for processing communication data, a packet counter 10 for discriminating between the presence and absence of communication data under process in the packet processing section 30, and a clock controller 40 for inputting or halting a clock signal to the packet processing section 30 in response to an output of the packet counter 10.
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