| 摘要 |
PURPOSE: A method for improving the operation speed of a digital equalizer using a pipeline is provided to achieve the speed enhancement without altering hardware structure by controlling the digital equalizer utilizing a pipeline technique. CONSTITUTION: A method for improving the operation speed of a digital equalizer using a pipeline includes a step of waiting for a request for a control signal(S410), a step of judging whether the control signal is requested and returning to the waiting step when the control signal is not requested(S420), and a step of encoding command data in a plurality of finite state machines to generate a plurality of control signals when the control signal is requested, and then returning to the waiting step(S430). The control signals include a buffer load enable signal, the first, second, and third MUX select signals, a register load signal, an adder/subtracter enable signal, and an accumulator load signal.
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