发明名称 System and method for reducing over-shoot and ringback by delaying input and establishing a synchronized pulse over which clamping is applied
摘要 In one embodiment of the invention, a clamping circuit clamps an input signal to reduce overshoot and ringback. A pulse generator generates a pulse signal having a pulse interval from the input signal and a delayed signal. The input signal transitions from a first level to a second level. The delayed signal is derived from the input signal. A controller generates a control signal responsive to the pulse signal. A switching circuit clamps one of the overshoot and the ringback of the input signal within the pulse interval upon receipt of the control signal.
申请公布号 US6694444(B1) 申请公布日期 2004.02.17
申请号 US20000608719 申请日期 2000.06.30
申请人 INTEL CORPORATION 发明人 MANDAL SUBRATA
分类号 G06F13/40;(IPC1-7):G06F1/30 主分类号 G06F13/40
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