发明名称 Method for saving power in a computer by idling system controller and reducing frequency of host clock signal used by system controller
摘要 A computer system has a central processing unit (CPU), a memory, a first power management routine, a second power management routine, a clock generator, an event controller, and a system controller for implementing a bus. The system controller uses a host clock signal that determines the operating frequency of the bus. The clock generator generates the host clock signal. The first power management routine has computer code that saves state information of the computer system in the memory and that places the system controller into an idle state. The second power management routine restores the computer system using the state information stored in the memory. The event controller sends an interrupt to the system controller to cause the CPU to execute the first power management routine, causes the clock generator to change the host clock signal to a new frequency while the system controller is in the idle state, activates the system controller after the host clock signal has changed to the new frequency, and causes the CPU to execute the second power management routine. By changing the host clock signal to the new frequency when the system controller is in the idle state, the event controller prevents the system controller from crashing. By changing the frequency of the host clock signal, the operating frequency of the bus is changed, and by changing the operating frequency of the bus the total power consumption of the computer system is changed.
申请公布号 US6694442(B2) 申请公布日期 2004.02.17
申请号 US20000737953 申请日期 2000.12.18
申请人 ASUSTEK COMPUTER INC. 发明人 YEH SHIH-PING
分类号 G06F1/32;(IPC1-7):G06F1/26;G06F1/04 主分类号 G06F1/32
代理机构 代理人
主权项
地址