发明名称 Method of testing integrated circuitry at system and module level
摘要 A method of testing integrated circuitry at a module and system level, in which an intermediate test, including multiple testing steps, is generated in a third programming language. The intermediate test is converted into an abstract representation of the testing steps. System and module level tests based on the abstract representation are generated in second and first respective programming languages. The integrated circuitry is then tested at system level with the system-level test and at module level with the module level test.
申请公布号 US6694497(B2) 申请公布日期 2004.02.17
申请号 US20010010962 申请日期 2001.10.26
申请人 STMICROELECTRONICS LIMITED 发明人 PAVEY NICHOLAS
分类号 G01R31/3183;(IPC1-7):G06F17/50 主分类号 G01R31/3183
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