发明名称 System and method of video frame memory reduction of video decoders
摘要 Embodiments of the invention comprise a new device and method to realize an improved video frame memory reduction for a video decoder. In one embodiment, this improvement is achieved by a removal of the rate controller and the utilization of both a block compression technique and a fixed storage allocation technique, in order to lower the overall system cost, and to lower the frame memory requirements. In a preferred embodiment, this improvement is achieved by performing a hierarchical transform, for example, a Haar transform, that operates on the previously decoded frames. Then, the coefficients obtained from this transformation are quantized and then run-length coded, utilizing variable-length codes. The hierarchical transform preferably operates on an NxN block size with L levels of hierarchical decomposition, where N and L can be selected in advance. For example, in one preferred embodiment, N may equal 8, and L may equal 3. The compression system then fits the NxN block into an allocated storage of (NxN)/cf bytes, where cf designates the compression factor. For example, a nominal value of cf that equals 2, 3, or 4 may be utilized. The quantization process comprises a simple scaling of the coefficients. However, the DC coefficient is not scaled. The variable-length encoder comprises a run-length encoder that fits as many coefficients as is possible into the available space of the (NxN)/cf bytes.
申请公布号 US6693961(B1) 申请公布日期 2004.02.17
申请号 US20000480225 申请日期 2000.01.10
申请人 CONEXANT SYSTEMS, INC. 发明人 AZADEGAN FARAMARZ
分类号 H04N7/26;(IPC1-7):H04B1/66;A06K9/36;H04N7/12 主分类号 H04N7/26
代理机构 代理人
主权项
地址
您可能感兴趣的专利