发明名称 |
Digital-to-analog DAC-driven phase-locked loop PLL with slave PLL's driving DAC reference voltages |
摘要 |
A clock generator uses two PLL loops and a digital-to-analog converter (DAC) to generate a variable output frequency from a single fixed-frequency reference clock. Each PLL loop receives the reference clock and phase-compares it with a feedback clock. The feedback clock in one loop is slightly faster in frequency than the feedback clock in the second loop. The input voltages to voltage-controlled oscillators (VCOs) in the two loops thus vary slightly. A DAC is connected between the two VCO inputs. The DAC's two reference-voltage inputs are connected to these VCO inputs. The DAC's output voltage is selected from within the voltage range between the two VCO voltages by a digital code-word input to the DAC. The DAC's output voltage is input to a final VCO that generates the variable output frequency. The output frequency is varied by selecting the digital code-word input to the DAC.
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申请公布号 |
US6693987(B1) |
申请公布日期 |
2004.02.17 |
申请号 |
US20000679682 |
申请日期 |
2000.10.05 |
申请人 |
PERICOM SEMICONDUCTOR CORP. |
发明人 |
HATTORI HIDE |
分类号 |
H03L7/089;H03L7/23;(IPC1-7):H03D3/24 |
主分类号 |
H03L7/089 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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