发明名称 METHOD FOR FORMING METAL INTERCONNECTION OF SEMICONDUCTOR DEVICE BY MODIFIED DUAL DAMASCENE PROCESS
摘要 PURPOSE: A method for forming a metal interconnection of a semiconductor device by a modified dual damascene process is provided to avoid a defect of an interconnection by preventing a recess in a via contact of a single damascene structure. CONSTITUTION: The first interlayer dielectric and the first and second material layers are sequentially formed on a semiconductor substrate(100) with a conductive layer(105) such that the first and second material layers include a material that reacts with a medium used in a process for eliminating photoresist. A photoresist layer of a pattern exposing a part of the upper surface of the second material layer is formed on the second material layer. The second material layer, the first material layer and the first interlayer dielectric are etched to form a via hole(160) by using the photoresist layer as an etch barrier layer(110). A part of the first material layer exposed to the via hole is changed while the photoresist layer is eliminated. The changed first material layer(135) is removed to form an opening larger than the via hole in the first material layer. The remaining second material layer is removed. A metal material is deposited to fill the via hole and the opening. A planarization process is performed until the first interlayer dielectric is exposed, so that a via contact is formed.
申请公布号 KR20040013165(A) 申请公布日期 2004.02.14
申请号 KR20020045610 申请日期 2002.08.01
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM, JAE HAK;LEE, GYEONG U;LEE, SU GEUN
分类号 H01L21/28;H01L21/768;(IPC1-7):H01L21/28 主分类号 H01L21/28
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