| 发明名称 |
MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
| 摘要 |
PURPOSE: To provide a method for manufacturing a semiconductor integrated circuit device provided with a fine pattern formation without causing increase in a chip cost and deterioration of throughput. CONSTITUTION: This manufacturing method for the semiconductor integrated circuit device comprises a step for patterning a gate(electrode or wiring). After patterning a hard mask on a gate with a resist mask, it is removed. Then, using the hard mask, a side surface of a gate material is thinned under a dry etching condition leaving no reaction product on the side surface of the gate material, to form an I-type gate. |
| 申请公布号 |
KR20040014112(A) |
申请公布日期 |
2004.02.14 |
| 申请号 |
KR20020054449 |
申请日期 |
2002.09.10 |
| 申请人 |
HITACHI HIGH-TECHNOLOGIES CORPORATION;KABUSHIKI KAISHA HITACHI SEISAKUSHO(D/B/A HITACHI, LTD.) |
发明人 |
MORI MASAHITO;TSUTSUMI TAKASHI;IZAWA MASARU;ITABASHI NAOSHI |
| 分类号 |
H01L21/265;H01L21/28;H01L21/3065;H01L21/3213;H01L21/336;H01L21/66;H01L29/423;H01L29/49;H01L29/51;H01L29/78;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/265 |
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