发明名称 MASTER SLAVE FLIP FLOP CIRCUIT
摘要 PURPOSE: To reduce power consumption of a master slave flip flop circuit. CONSTITUTION: The circuit employs a configuration comprising a master latch circuit 6 for switching data to a through or holding status, a slave latch circuit 7 for switching data to a holding or through status, and a circuit setup control means 3 for setting the master latch circuit 6 to a through status and the slave latch circuit 7 to a holding status or setting the master latch circuit 6 to the holding status and the slave latch circuit 7 to the through status using "L" and "H" of an clock signal CLK1, respectively. According to the configuration, the number of transistors for operating by a change in the clock signal is decreased, and electric power consumption at a gate electrode is reduced.
申请公布号 KR20040014160(A) 申请公布日期 2004.02.14
申请号 KR20030023983 申请日期 2003.04.16
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA;MITSUBISHI ELECTRIC SYSTEM LSI DESIGN CORPORATION 发明人 ARAKI MASAHIRO
分类号 H03K3/356;H03K3/3562;(IPC1-7):H03K3/356 主分类号 H03K3/356
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