| 摘要 |
PURPOSE: To provide a readout circuit for memory cell information and a semiconductor memory device using this, which can execute memory cell read operation at a high speed. CONSTITUTION: A feedback bias circuit 3 stabilizes bit-line potential at a designated potential, by restraining the amount of current flowing through a bit-line BL driven by a load circuit 4. A comparator circuit 5, connected to the bit-line BL, through which the memory cell information is transmitted, compares a voltage value corresponding to the current value flowing through the bit-line BL driven by the load circuit 4, with a reference voltage and read out the value for the memory cell information from its output terminal. A precharge circuit 6 discharges electric charges charged on the bit-line BL, when a drive voltage applied on the bit-line BL from the load circuit 4 exceeds the designated potential. A bit-line leakage circuit 7 supplies charge current to the bit-line BL, based on external charge start signal and shuts off the charge current on the bit-line BL, when the drive current applied from the load current circuit 4 exceeds the designated potential.
|
