发明名称 PARALLEL OUTPUT TYPE ELECTRONIC INTERLOCKING SYSTEM FURNISHED WITH FAIL SAFE MAJORITY LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a fail safe majority logic circuit not to output false output on the dangerous side even at the time when a single failure occurs by discovering the single failure at an early stage. SOLUTION: The fail safe majority logic circuit to find a majority of at least three pieces of logic input is constituted by a circuit to compose the two input each of the three input of three pieces of OR circuits 311∼313 and to compose output of these OR circuits by a three input AND circuit 321. Additionally, a control mode and a failure detection mode are set in the circuit, a pattern for failure detection is input at the time of the failure detection mode and a failure of a part constituting the circuit is detected by absorbing the output. The input is forcibly changed so that the output of the circuit does not output to the dangerous side in the case of detecting the failure. Safety of the electronic interlocking device is improved by applying this fail safe majority logic circuit to the electronic interlocking device. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004042906(A) 申请公布日期 2004.02.12
申请号 JP20030343270 申请日期 2003.10.01
申请人 HITACHI LTD;EAST JAPAN RAILWAY CO 发明人 KAWABATA ATSUSHI;TASHIRO FUSASHI;FUJIWARA MICHIO;YANAGI HITOSHI;KUWANA SHIGERU;KIKUCHI TSUNENOBU;FUKUI SATOSHI;SAITO HIROSHI
分类号 B61L19/06;G05B9/02;(IPC1-7):B61L19/06 主分类号 B61L19/06
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