| 摘要 |
An integrated circuit comprising a main section/processor and a subsection/subprocessor for debugging the main section is provided with hardware modules coupled via a subbus to said subprocessor and coupled to different parts of said main section, for debugging more directly. The hardware modules comprise a shiftregister coupled to a chain unit and a clock controller coupled to a clock generator for scanning purposes, a scan controller coupled to said chain unit for selection scanning options, a breakpoint controller coupled to said chain unit for interrupting said scanning, and/or a programmable register coupled to dedicated hardware for tracing purposes. An access module is coupled to an interface for communication with the outside world and is further coupled to an access memory. A subprocessor memory stores amendable/replacable software for controlling said subsection and said debugging as well as a transmission of debugging results via said access module to an external debugger.
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