| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a circuit for generating a clock which decreases clock cycles required for phase locking between an internal clock signal and an external clock signal. <P>SOLUTION: A phase difference between a feedback clock signal FBCLK, which corresponds to the internal clock signal (CLKP, CLKN) generated through variable delay lines (32, 33), and a buffer clock signal (BUFCLK) corresponding to the external clock signal is detected and the detected result is transfered via a shift circuit (42) to an outside. A down instruction signal (DWN) is forcibly maintained in an active state for a predetermined period of the clock cycles, if the down signal from the shift circuit (42) is activated by a delay control circuit (20). A count control circuit (41) sets a unit for counting of a count circuit (37) in a minimum value if the state of down instruction signal changes from the state of activated to the state of non-activated. A variable delay line sets a delay amount in accordance with an output count bit (A[N:0]) of a count circuit. <P>COPYRIGHT: (C)2004,JPO |
