发明名称 MANUFACTURING METHOD FOR MULTILAYER WIRING SUBSTRATE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a multilayer wiring substrate in which the multilayer wiring substrate of a fine wiring pattern pitch of 10μm or less is manufactured at a low cost, the occurrence of inconsistency in a photolithography process due to warping is prevented, and a problem that a manufacturing process extends over a long period of time due to a long etching time is prevented. <P>SOLUTION: A multilayer wiring structure is formed on a flat metal plate 1. Then the metal plate 1 is removed by etching all over the surface, to leave only a multilayer wiring layer 9. An insulating substrate 11 having an aperture 12 and the multilayer wiring layer 9 are bonded together. Then the apertured part 12 is filled with a conductive adhesive 13, to mount a semiconductor chip 14 and to join a solder ball 17. <P>COPYRIGHT: (C)2004,JPO</p>
申请公布号 JP2004048045(A) 申请公布日期 2004.02.12
申请号 JP20030318607 申请日期 2003.09.10
申请人 NEC ELECTRONICS CORP 发明人 HONDA KOICHI
分类号 H05K3/46;H01L23/12;(IPC1-7):H05K3/46 主分类号 H05K3/46
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