发明名称 INTER-BLOCK INTERFACE CIRCUIT AND SYSTEM LSI
摘要 PROBLEM TO BE SOLVED: To effectively prevent any inconvenience(the generation of through-currents due to the potential inequality of wiring) due to the power off of a block by a simple circuit in an LSI where inter-block signal transmission is executed, and the power sources of the blocks are independently interrupted. SOLUTION: BLocks 12 and 14 for transferring signals are respectively provided with gate circuits 70 and 80, and the input levels of the gate circuits 70 and 80 are dynamically controlled by an interface control circuit 300. That is, the input levels of gate circuits 70 and 80 at a power ON side are fixed to an "L" level so that the outputs of the gate circuits can be forcedly fixed to the "L" level. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004048370(A) 申请公布日期 2004.02.12
申请号 JP20020202850 申请日期 2002.07.11
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MOGI ISAO;NAGATA EIJI
分类号 H01L21/822;H01L27/04;H03K19/00;(IPC1-7):H03K19/00 主分类号 H01L21/822
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