发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS LAYOUT METHOD
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which design flexibility is enhanced and the number of I/O buffers (number of signals) can be increased while suppressing an increase in dead space or area of a substrate. SOLUTION: A semiconductor integrated circuit device comprising an area I/O 3, a macro 4 and a peripheral I/O 2 is employed. The area I/O 3 is arranged at an arbitrary position in a gate region 5 on a chip 1 or on the periphery thereof and includes a plurality of I/O buffers. The macro 4 is arranged at an arbitrary position in the gate region 5. The periphery I/O 2 includes a plurality of I/O buffers arranged on the periphery thereof. The macro 4 is combined with the area I/O 3 which is used therein and arranged at an arbitrary position thereof. Furthermore, a plurality of logic gates are arranged in the gate region 5. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004047516(A) 申请公布日期 2004.02.12
申请号 JP20020199192 申请日期 2002.07.08
申请人 NEC ELECTRONICS CORP 发明人 SONOHARA HIDEO
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/02;H01L27/04;(IPC1-7):H01L21/822 主分类号 G06F17/50
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