| 摘要 |
PROBLEM TO BE SOLVED: To provide a sample-and-hold circuit which can stabilize an output while avoiding the reduction of the operational speed of the circuit and preventing the increase of a circuit scale, and can avoid the influences on the output even when an extent of change in the output becomes large. SOLUTION: The sample-and-hold circuit includes a differential pair M<SB>1</SB>, M<SB>2</SB>as an input stage, a tail current source for the differential pair, and a sampling capacitance. The tail current source for the differential pair M<SB>1</SB>, M<SB>2</SB>has two divisions I<SB>tail</SB>/2, I<SB>tail</SB>/2. A switch SW<SB>2</SB>is provided between the two division tail current sources I<SB>tail</SB>/2, I<SB>tail</SB>/2. In a hold mode, the switch SW<SB>2</SB>is disconnected so that a series connection of circuits of parasitic capacitances C<SB>gs1</SB>, C<SB>gs2</SB>between the gates and sources of the pair M<SB>1</SB>, M<SB>2</SB>to the sampling capacitance C<SB>s</SB>can be avoided. COPYRIGHT: (C)2004,JPO
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