发明名称 OPTIMIZING MERGEABILITY AND DATAPATH WIDTHS OF DATA-FLOW-GRAPHS
摘要 A DFG (100) has inputs A and B linked by edges (140) and (150), respectively, to an operator NI illustrated at (125). DFG (100) has inputs C and D linked by edges (145) and (160), respectively, to an operator N2 illustrated at (130). Operators NI and N2 (125) and (130) are illustrated as addition operators but could any of a variety of types of operators. The bitwidths of edges (140, 145, 150 and 160) are equal to 8. The widths of operators N1 and N2 (125) and (130) are equal to 9. While an output edge (155) has a bitwidth of 9. Which corresponds to the operator N2 (130), that of an output corresponds to the output of operator N2 (130) that of an output edge (165) which corresponds to the output of operator N1 (125), is equal to 7 so the output of node N1 (125) is obtained by truncating a 9 bit result to 7 bits by the operator N1 (125).
申请公布号 WO02103483(A3) 申请公布日期 2004.02.12
申请号 WO2002US19138 申请日期 2002.06.17
申请人 CADENCE DESIGN SYSTEMS, INC.;SALUJA, SANJEEV;MATHUR, ANMOL 发明人 SALUJA, SANJEEV;MATHUR, ANMOL
分类号 G06F9/44;G06F9/45;G06F17/50 主分类号 G06F9/44
代理机构 代理人
主权项
地址