| 摘要 |
PROBLEM TO BE SOLVED: To reduce a size of a chip component by shrinking a size of a via hole 5. SOLUTION: Between coil patterns 3a and 3b, a plurality of insulating thin layers 7 are stacked to form an insulating layer 4. In a process of forming the insulating layer 4, first, an insulating material for an insulating thin film 7a is stacked on the coil pattern 3a. After forming a via hole 8a in the insulating material layer, the insulating material layer is baked into the insulating thin layer 7a. In such a manner, an insulating material for an insulating thin layer 7b is stacked on the insulating thin layer 7a, and a via hole 8b is formed in the insulating material layer. Thereafter, the insulating material layer is baked into the insulating thin layer 7b. Each time the insulating material for the insulating thin layer 7 is stacked, a via hole 8 is is formed in the insulating material layer and then the insulating material layer is baked, making the insulating material layer at the time of baking thin. As the insulating material layer becomes thinner, the expansion of the via hole 8 due to baking can be suppressed low, leading to the shrinkage of the via hole 5. COPYRIGHT: (C)2004,JPO
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