| 摘要 |
PROBLEM TO BE SOLVED: To provide a stable memory control circuit which has no possibility of generating an interfering radio wave to other equipment or never attenuates the waveform of a memory control signal or clock signal. SOLUTION: This circuit comprises a memory controller for controlling a memory; a drive current variable driver for driving a memory address bus and the memory control signal; a DIMM (dual in-line memory module) having a memory module; a DIMM detecting circuit for detecting the loaded capacity of the DIMM; a drive current setting circuit for setting the driving capacity of the driver; and a CPU. The driving capacity of the driver is automatically adjusted in conformation to the capacity of the memory to be loaded, whereby the clock, address bus or memory control signal waveform is suitably set. Accordingly, a memory control circuit stabilized in circuit operation can be constituted. COPYRIGHT: (C)2004,JPO
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