发明名称 |
Method and apparatus for implementing two architectures in a chip |
摘要 |
The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexer or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.
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申请公布号 |
US2004030865(A1) |
申请公布日期 |
2004.02.12 |
申请号 |
US20030602916 |
申请日期 |
2003.06.25 |
申请人 |
KNEBEL PATRICK;SAFFORD KEVIN DAVID;SOLTIS DONALD CHARLES;LAMB JOEL D;UNDY STEPHEN R.;BROCKMANN RUSSELL C. |
发明人 |
KNEBEL PATRICK;SAFFORD KEVIN DAVID;SOLTIS DONALD CHARLES;LAMB JOEL D;UNDY STEPHEN R.;BROCKMANN RUSSELL C. |
分类号 |
G06F9/318;G06F9/38;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/318 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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