发明名称 High performance IP processor
摘要 An architecture provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol Layer and may also provide packet inspection through Layer 7. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory.
申请公布号 US2004030757(A1) 申请公布日期 2004.02.12
申请号 US20030459297 申请日期 2003.06.10
申请人 PANDYA ASHISH A. 发明人 PANDYA ASHISH A.
分类号 G06F15/173;G06F15/177;H04L29/06;H04L29/08;(IPC1-7):G06F15/16 主分类号 G06F15/173
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