| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of testing high-speed time performance by using a low-speed tester. <P>SOLUTION: A test mode decision circuit 12 sets a test mode in the semiconductor memory. A command decoder 2 synchronizes with an external clock signal CLK when the test mode is set in the semiconductor memory, and sequentially generates an internal control signal that is similar to that when a plurality of commands are inputted in a normal mode at predetermined timing in response to a prescribed external control signal (command) inputted from a control input terminal (/RAS, /CAS, /WE, and /CS). <P>COPYRIGHT: (C)2004,JPO</p> |
