发明名称 |
System and method for determining on-chip bit error rate (BER) in a communication system |
摘要 |
A test packet generator (225a) within a physical layer device (230) may generate test packets to be communicated over a closed communication path established within the physical layer device (230). The test packets may include a pseudo-random bit sequence. A receiver within the physical layer device (230) may receive at least a portion of the generated test packet. A test packet checker (225b) within the physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine the bit error rate for the physical layer device. A window counter (225c) within the physical layer device (230) may count at least a portion of a number of bits received within the generated test packets and a number of bits that are in error in at least a portion of the number of bits received. Accordingly, the bit error rate may be calculated based on a ratio of the number of counted bits in error to the number bits counted in the at least a portion of the number of bits received.
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申请公布号 |
US2004030968(A1) |
申请公布日期 |
2004.02.12 |
申请号 |
US20020291078 |
申请日期 |
2002.11.08 |
申请人 |
FAN NONG;HOANG TUAN;JIANG HONGTAO |
发明人 |
FAN NONG;HOANG TUAN;JIANG HONGTAO |
分类号 |
H04L1/20;H04L1/24;(IPC1-7):G06F11/00 |
主分类号 |
H04L1/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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