| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an arithmetic unit by which addition accumulation processing for product is simply materialized by improving an ordinary product sum arithmetic unit and an increase in power consumption is controlled to the minimum without complicating circuit configurations. <P>SOLUTION: Product sum operation is conducted to input data A, B, C by using a multiply accumulator 100 to output the operation result D1 of AxB+C. In the second and the successive processing, the operation result D1 of the multiply accumulator 100 is selected by a selector 150 to retain the operation result D1 in a register 166. In the multiply accumulator 100, the product of newly inputted data A and B is calculated to add the product to the data retained in the register 166. Repeating the multiply accumulation processing by the frequency of specified operation materializes the addition and accumulation processing to the product sum operation result by a simple hardware configuration. <P>COPYRIGHT: (C)2004,JPO |
