| 摘要 |
A self-synchronous FIFO memory device (100) has a structure in which n self-synchronous data transmission lines (111-11n) are arrayed in parallel. An input control section (101) selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a first transfer request signal, a first acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a preceding-stage section. Further, an output control section (102) selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a second transfer request signal, a second acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a succeeding-stage section.
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