| 摘要 |
PURPOSE: A data output circuit of a synchronous semiconductor memory device is provided to minimize junction loading and interconnection loading and data skew. CONSTITUTION: According to the data output circuit of a synchronous semiconductor memory device comprising a data output multiplexer having a wave pipeline structure, every output port of two register output selection switches is connected to a multiplexing output line through a single line, by forming output part active regions of adjacent register output selection switches(S1,S2,S3,S4,S5,S8,S9,S10,S12,S13,S16) in common, in order to reduce junction loading of the multiplexing output line connected to lines connected to output ports of register output selection switches in the above data output multiplexer in common. The above register output selection switches are constituted with a CMOS transmission gate respectively.
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