| 摘要 |
The memory store of type SRAM comprises an array of memory cells, and each cell comprises 6 transistors connected so to form two inverters and two interrupters of the cell. The inputs of two inverters are connected to two bit lines (BL0,/BL0) by the intermediary of interrupters which are in the form of transistors controlled by a signal delivered by one of two word lines (WL0,WL1). Each memory cell comprises two first regions of n-type conductivity, where each region comprises the drains and the sources of one first transistor (N1,N2) and one third transistor (A1,A2). The first regions are in contact with second mutually adjacent regions of p-type conductivity, where each comprises the drain and the source of one second transistor (P1,P2). The first and the second regions are short-circuited by a layer of conducting material, and the strip conductors (42,43,44,45) parallel to the bit lines make connections between the inverters and between the interrupters and the word line. Each cell 6T comprises 6 transistors (N1,P1,A1,N2,P2,A2) whose gates (GN1,GP1,GA1,GN2,GP2,GA2) are at the same level of conducting material, and whose interconnections are implemented by strip conductors of another conducting material distributed on 3 levels. Each inverter comprises 2 transistors, one first transistor (N1,N2) of n-type conductivity and one second transistor (P1,P2) of p-type conductivity, and each interrupter comprises one third transistor (A1,A2) of n-type conductivity. The two word lines (WL0,WL1) correspond to metallic strips at the level 2 or 3, and the word lines are associated with a row of cells where each cell is connected to one of the two word lines. The bit lines (BL0,/BL0) correspond to metallic strips perpendicular to the word lines and are at a level different from the level of the word lines. The strip conductors (44,45) connect one of the word lines (WL0,WL1) to one third transistor (A1,A2). The sources and the drains of first transistors (N1,N2) and third transistors (A1,A2) are aligned to the bit lines. Each cell comprises two active zones (29,30) and each active zone comprises one of the first regions and the associated second region. The active zones are substantially symmetric with respect to the center of the cell. Each memory cell placed between two other memory cells of the same row is connected to two supply voltages (GND,VDD), where two supply lines (GND) are shared between two neighboring cells. |
