发明名称 |
Method and apparatus for 24-bit memory addressing in microcontrollers |
摘要 |
The present invention provides an 8-bit microcontroller capable of supporting expanded addressing capability in one of three address modes. The microcontroller operates in either the traditional 16-bit address mode, a 24-bit paged address mode or in a 24-bit contiguous address mode based on the setting of a new Address Control (ACON) Special Function Register (SFR). The 24-bit paged address mode is binary code compliant with traditional compilers for the standard 16-bit address range, but allows for up to 16M bytes of program memory and 16M bytes of data memory to be supported via a new Address Page (AP) SFR, a new first extended data pointer (DPX) SFR and a new second extended data pointer (DPX1) register. The 24-bit contiguous mode requires a 24-bit address compiler that supports contiguous program flow over the entire 24-bit address range via the addition of an operand and/or cycles to either basic instructions.
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申请公布号 |
US6691219(B2) |
申请公布日期 |
2004.02.10 |
申请号 |
US20010924249 |
申请日期 |
2001.08.07 |
申请人 |
DALLAS SEMICONDUCTOR CORPORATION |
发明人 |
MA EDWARD TANGKWAI;TAYLOR, III FRANK V.;GRIDER STEPHEN N.;LITTLE WENDELL L. |
分类号 |
G06F12/00;G06F13/00;G06F15/78;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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