| 摘要 |
A delay locked loop (DLL) circuit (10) can include first phase decision circuit (1), a second phase decision circuit (2), an arbitrary phase generator circuit (3), and a variable pulse width circuit (4). First phase decision circuit (1) may receive an external clock signal (D1) and an internal clock signal (D3) and may generate a phase decision signal (D4) that may indicate whether a first edge of internal clock signal (D3) is to be sped-up or delayed. Arbitrary phase generator circuit (3) may provide a phase shifted signal based on phase decision signal (D4). Second phase decision circuit (2) may receive external clock signal (D1) and internal clock signal (D3) and may generate a phase decision signal (D5) that may indicate whether a second edge of internal clock signal (D3) is to be sped-up or delayed. Variable pulse width circuit (4) may receive the phase shifted signal and delay a falling edge based on phase decision signal (D5).
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