| 摘要 |
A clock generation circuit and device are disclosed for reading/writing information from to/an information carrier. The clock generation circuit includes a frequency divider for generating a first intermediate clock signal from an input clock signal. A first logical unit combines the input clock signal and the intermediate clock signal. The circuit further includes a clocked bistable unit having a clock input coupled to an output of the first logical unit, and a data input and a data output, and a second logical unit having a selection input for receiving a synchronization signal from a synchronization module having an input for receiving a reference clock signal. The synchronization signal controls selection between a feedback mode and a reset mode. In the feedback mode, the second logical unit logically inversely couples the data input to the data output, and in the reset mode the second logical unit provides a reset value to the data input. The data output provides the output clock signal.
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