发明名称 |
Vertical replacement-gate junction field-effect transistor |
摘要 |
A vertical JFET architecture. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is disposed over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.
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申请公布号 |
US6690040(B2) |
申请公布日期 |
2004.02.10 |
申请号 |
US20010950384 |
申请日期 |
2001.09.10 |
申请人 |
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发明人 |
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分类号 |
H01L21/337;H01L21/8232;H01L21/8234;H01L27/06;H01L27/088;H01L27/095;H01L27/098;H01L29/78;H01L29/80;H01L29/808;(IPC1-7):H01L29/32;H01L29/74;H01L31/111;H01L29/423;H01L31/032;H01L31/033;H01L31/072;H01L31/109;H01L29/73;H01L31/112;H01L29/76;H01L29/94;H01L31/062;H01L31/113;H01L31/119 |
主分类号 |
H01L21/337 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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