发明名称 |
High speed pre-computing circuit and method for finding the error-locator polynomial roots in a Reed-Solomon decoder |
摘要 |
A system and method used in a Reed-Solomon (RS) decoder for determining roots of error locator polynomials in which a first pre-computation operation is performed to obtain a p-bit polynomial solution value in a first clock cycle and second parallel feedback logical operations are performed to obtain a p-bit polynomial solution value in each subsequent clock cycles. The system excludes constant Galois Field multipliers from the critical timing path of the system so as to facilitate high speed error-locator polynomial root determination. In the case of an unshortened RS(m,d) decoder defined over the Galois Field GF(2<p>) where GF(2<p>) is a finite field of 2<p >elements and m=2<p>-1, final root location values are obtained in m cycles. In the case of a shortened RS(n,d) decoder defined over the Galois Field GF(2<p>) where GF(2<p>) is a finite field of 2<p >elements and m=2<p>-1 and n<m, final root location values are obtained in n cycles.
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申请公布号 |
US6691277(B1) |
申请公布日期 |
2004.02.10 |
申请号 |
US19980190149 |
申请日期 |
1998.11.12 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
GOLNABI HABIBOLLAH;DEOL INDERPAL |
分类号 |
G06F11/10;H03M13/15;(IPC1-7):H03M13/15 |
主分类号 |
G06F11/10 |
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