| 摘要 |
<p>A semiconductor memory device includes a plurality of cell blocks each having a plurality of memory cells, a plurality of bit lines for reading data from the individual memory cells, and a precharge circuit for precharging one bit line selected from among the plurality of bit lines in response to a precharge signal. It is determined whether charge in the precharged bit line is to be discharged based on a data content of a memory cell in the cell block selected by a row decoder connected to the bit line. The data content of the selected memory cell in the selected cell block is read out by a potential of the bit line. The memory device further includes at least one gate switching element connected in series to the memory cells of each of the cell blocks. The gate switching element, together with the memory cells of each cell block, forms a series circuit which has one end connected to an associated one of the bit lines and a second end connected to a low-voltage power supply. A mode setting circuit enables the gate switching element during precharging in a fast data reading mode, and disables the gate switching element during precharging in a slow data reading mode.</p> |
