发明名称 Boosting circuit configured with plurality of boosting circuit units in series
摘要 By supplying a clock signal from an OSC to four stages of boosting circuit units connected in series, the boosting circuit units are rendered active. A delay element is inserted in the line of the clock signal to prevent all the boosting circuit units from being rendered active at the same time by one clock signal. Since the boosting circuit unit is rendered active one by one by the provision of the delay element, current congregation from the power supply potential at the circuit element connected closest to the input terminal of the boosting circuit unit of the first stage can be prevented. Thus, a boosting circuit of a high boosting efficiency is achieved.
申请公布号 US2004021504(A1) 申请公布日期 2004.02.05
申请号 US20030339327 申请日期 2003.01.10
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 MIHARA MASAAKI
分类号 H02M3/07;(IPC1-7):G05F1/10 主分类号 H02M3/07
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